As technology advances, and the dimensions of transistor devices continue to shrink, difficulty increases with respect to maintaining lithographic printability of designs for fabrication of semiconductor devices. For example, a known SRAM bit cell 100 in FIG. 1A includes metal1 landing pads 101 for word lines, metal1 landing pads 103 for ground lines, and metal1 bit line structures 105, and metal2 layer structures 107. In addition, bit cell 100 includes active region contacts 109, metal contacts 111, and via1 structures 113 for performing various interconnections associated with the metal1 layer structures 101, 103, and 105, and the metal2 layer structures 107. However, bit cell 100 may be difficult to print on a wafer because metal structures of the same color (or patterning) in bit cell 100 are too close to each other. As shown, for instance, word line landing pads 101 may be too close to ground line landing pads 103, and landing pads 101 and 103 may be too close to bit line structures 105. As such, it may become increasingly difficult to further shrink the design of bit cell 100. Moreover, as illustrated by another known SRAM bit cell 130 in FIG. 1B, single patterned metal lines (e.g., metal1 layer structures 131 and 133) occupy significant space. However, if the height of bit cell 130 is reduced (e.g., to decrease the space occupied), the tip-to-tip spacing between metal1 layer structures 133 (in which the tip is the short side of the structure), particularly in same color space, will become too close, negatively affecting lithographic printability of bit cell 130.
A need therefore exists for a miniaturized SRAM bit cell with improved lithographic printability, and enabling methodology.